1. Field of the Invention
This invention relates to the field of semiconductor processing and, more particularly, to an integrated circuit and method of making the same in which a layer of varying thickness is deposited upon a topographical surface of a semiconductor topography to compensate for elevational variations across the surface.
2. Description of Relevant Art
An integrated circuit consists of electronic devices electrically coupled by conductive trace elements, i.e., interconnect. Interconnect are patterned from conductive layers formed above the surface of a semiconductor substrate in which impurity regions have been formed. An integrated circuit can comprise multiple levels of interconnect spaced from each other by interlevel dielectric layers and electrically linked by contact structures extending through the interlevel dielectric layers. The use of multiple levels of interconnect within an integrated circuit increases the density of active devices placed upon a single monolithic substrate.
In addition to added process complexity, an increase in the number of interconnect levels leads to a corresponding increase in the elevational disparity of the resulting surface (i.e., an increase in the difference between the peaks and valleys of the resulting upper surface). For example, when a dielectric layer is chemically-vapor deposited across interconnect lines laterally spaced from each other within a single horizontal plane, numerous peaks and valleys may result in the upper surface of the dielectric layer. The chemical-vapor deposition ("CVD") process produces a relatively conformal dielectric layer across the semiconductor topography comprising the interconnect lines. In this manner, the dielectric layer climbs to a higher elevation when it crosses over an interconnect line and falls to a lower elevation in between interconnect lines.
Unfortunately, elevation disparity across the upper surface of an ensuing integrated circuit can lead to many problems. Exemplary problems include stringers arising from incomplete etching over severe steps, failure to open vias due to interlevel dielectric thickness disparity, and poor adhesion to underlying materials. Elevation disparity also causes step coverage problems of, e.g., interconnect placed over an interlevel dielectric peak and valley area as well depth-to-focus problems when patterning, e.g., interconnect upon an interlevel dielectric. Many manufacturers have undergone extensive research in methods for planarizing topographical surfaces in order to avoid the above problems. Chemical-mechanical polishing ("CMP") is a well known technique used to planarize the surfaces of layers formed during integrated circuit fabrication.
A typical CMP process involves placing a semiconductor wafer face-down on a polishing pad which is fixedly attached to a rotatable table or platen. Elevationally extending portions of the downward-directed wafer surface contact with the rotating pad. A fluid-based chemical, often referred to as a "slurry" is deposited upon the pad possibly through a nozzle such that the slurry becomes disposed at the interface between the pad and the wafer surface. The slurry initiates the polishing process by chemically reacting with the surface material being polished. The polishing process is facilitated by the rotational movement of the pad relative to the wafer (or vice versa) to remove material catalyzed by the slurry. Unfortunately, if the reaction rate of the slurry with the surface material varies across the surface, certain areas of the wafer may be removed more quickly than others. Further, a CMP polishing pad which conforms to underlying surfaces, or bows in an arcuate pattern in response to force applied thereto, may undesirably remove some portions of the wafer while leaving others behind. Thus, reaction rate variation and/or pad pressure variation can lead to the formation of recesses in the topographical surfaces being "planarized" by CMP.
It would therefore be desirable to develop a process for substantially planarizing the upper surface of a semiconductor topography. Particularly, a process is needed which would minimize the surface disparity across a layer formed during the fabrication of an integrated circuit. A planarization process which does not result in the formation of recesses in the topographical surfaces being planarized would be beneficial. Such a process could be used as a replacement of a CMP planarization step, or in some cases as a back-up planarization step in addition to CMP.